The present invention deals broadly with the field of electrical interconnect systems, and relates generally to technology, for example, for interconnecting a lead of an integrated circuit device with a corresponding terminal on a printed circuit board interfacing with a test apparatus intended to effect test analysis of the integrated circuit device.
A plethora of applications exist for effecting electrical contact between two conductors. One significant application is effecting interconnection between leads of an integrated circuit device and conductive pads or terminals on a printed circuit (PC) board, which serves to create electrical contact between the integrated circuit (IC) device and a test apparatus. Such apparatus are used to evaluate performance of integrated circuit devices.
Numerous considerations bear upon the structure employed to interconnect the IC and the PC board. These factors include both electrical and mechanical considerations. For typical interconnection systems, special attention must be given to electrical performance, including self inductance and capacitance, the life span requirements, issues of repairability or replacability, the operation temperature environment, coplanarity of the device terminals, mechanical manufacturing limitations, and device alignment, including terminal orientation relative to the interconnection system.
In a typical semiconductor production facility, each IC is tested using a test apparatus. The test apparatus may be connected to an interconnection system wherein the leads of an IC are connected to a PC board within the interconnection system. The PC board may then be controlled by the test apparatus for testing the IC.
The test apparatus may test the functionality and performance of an IC through the interconnection system. Due to manufacturing process variations, some of the IC""s may perform at a higher level than other IC""s. Therefore, the test apparatus may be used to sort the devices according to their performance characteristics. This is termed xe2x80x9cspeed gradingxe2x80x9d. Typically, the higher performance IC""s will receive a premium price in the market place. It can readily be seen that it is important that the interconnection system not distort the performance characteristics of the IC under test. If it does, the IC manufacturer may lose a substantial amount of revenue.
One objective of an interconnection system is to maintain a xe2x80x9cnon-distorting electrical interconnectionxe2x80x9d between the test apparatus and the IC as discussed above. To accomplish this, it is a goal of an interconnection system to have low lead inductance/resistance, low lead-to-lead capacitance, low lead-to-ground capacitance, and a high electrical decoupling factor. These characteristics all reduce the xe2x80x9cdistortingxe2x80x9d nature of the electrical interconnection system.
Another objective of the interconnection system is to maintain a consistent and reliable electrical interconnection over many test cycles. In conventional interconnection systems, the contact resistance of the interconnection system may change after continued use. A cause of this resistance change may be solder buildup on the contacts within the interconnection system. Increased contact resistance can distort the performance of the IC and thus reduce the test yield realized.
Because of tolerances in the manufacturing process, all of the leads of a semiconductor package may not be coplanar. For similar reasons, contacts of the interconnection system itself may not be fully coplanar. Therefore, when the IC and the interconnection system are brought into engagement, some of the leads of the IC package may not be adequately contacted to corresponding contacts within the interconnection system. It is a goal of the interconnection system to compensate for these non-coplanarities.
To accomplish this, the interconnection system may comprise interconnection contact elements wherein the IC package leads contact and depress a corresponding contact in the interconnection system until the remaining package leads come into engagement with corresponding contacts. An advantage of this arrangement is that the movable contact elements allow each semiconductor lead to have a force applied thereon which falls within an acceptable range to establish a gas-tight connection, despite any non-coplanarity of the semiconductor package and interconnection system.
One prior art structure that seeks to accomplish the purpose of the present invention is a pogo-pin configuration. A pogo-pin configuration typically consists of a contact tip, a shaft, a barrel, and a spring. The shaft is enclosed within the barrel and biased by the spring to an upward position. Located at the upper tip of the shaft is the contact tip for contacting the lead of a semiconductor package. The shaft generally makes electrical contact with the barrel, and the lower portion of the barrel is connected to a PC board. As a semiconductor package lead comes into contact with the contact tip, the spring allows the shaft to depress downward into the barrel while still maintaining electrical contact with the barrel. The semiconductor package is forced down on the pogo-pins until all of the semiconductor package leads have an appropriate force thereon.
Although the pogo-pin configuration solves some of the problems discussed above, the leads are generally long and therefore inject a substantial amount of inductance into the interconnection system. Because of this relatively high level of inductance, the pogo-pin configuration may generally be limited to medium to low speed applications. Additionally, the piercing action utilized by the pogo-pin to make contact with a device (i.e., the action produced by the spring action applied to a small area) can be detrimental to the solderability later in the production process.
Another prior art structure that seeks to accomplish the purpose of the present invention is known as the Yamaichi contact. This type of contact includes an inverted L-shaped support having a cantilevered contacting portion mounted at the distal end of a generally horizontal leg of the inverted, L-shaped support and extending generally parallel to that leg. The distal end of the contacting portion is upwardly turned so that a point thereof is engageable by a lead of an IC device to be contacted. The support, in turn, is engaged in some manner with or through a pad or terminal portion of a printed circuit board. Problems that have been observed with the Yamaichi contact include solder buildup, difficulty of construction, and high inductance. In addition, the Yamaichi contact relies on the flexure of the contact material that creates an offset between the input/output feature on the IC under test and the circuit board.
Another type of structure that seeks to accomplish the purpose of the present invention is a fuzz button contact. A fuzz button contact typically consists of a specially designed array of resilient knitted wire mesh that is retained within a housing mounted to a PC board. The lead of a semiconductor package may be received by the housing, wherein the wire mesh forms a connection therewith. The fuzz button contact allows for some degree of compression that helps compensate for the non-coplanarity of the semiconductor package and the interconnection system. Due to the close contact of the wire mesh, a low resistance/inductance connection can be realized between the PC board and a lead of the semiconductor device. Typical problems with the fuzz button contact include the loss of compliance of the wire mesh after continued use. Furthermore, the wires within the wire mesh may become fatigued and eventually break. Finally, the wire mesh may become undesirably deformed, particularly if the fuzz button is over compressed. All of these problems limit the reliability and life expectancy of the fuzz button contact configuration.
Another prior art structure that seeks to accomplish the purpose of the present invention is a wire contact. A wire contact consists of a wire that is held in place by a housing. A first end of the wire is in contact with a PC board, and a second end of the wire is in contact with a lead of a semiconductor package. As the lead of the semiconductor package is forced down upon the second end of the wire, the center portion of the wire is bent in a lateral direction. The properties of the wire may be selected to provide the desired stiffness and deflection force.
Yet another prior art structure is a solid post contact (i.e., a conductive block or cylinder). Although electrical performance afforded is superior, such structures typically do not provide z-axis compliance or scrub. This puts the IC at risk for damage or signal degradation.
It thus remains highly desirable to provide a device that improves upon known methods, techniques and devices by providing: compliance in the z-axis, horizontal translation, large contact surface, and compact size. It is to these dictates and shortcomings of the prior art that the present invention is directed.
An interconnect contact device having cooperatively interfacing first and second contact elements and a resilient member disposed relative to the elements such that the resilient member biases the first contact element into engagement against the second contact element for responsive displacement of the first contact relative to the second contact element. Embodiments of the invention may be constructed to provide a wiping action at the cooperative interface between the elements and their connections to other devices. The device thereby provides for an integrated circuit connected thereto: compliance in the z-axis, horizontal translation, a large contact surface, and a compact size.
More specific features and advantages will become apparent with reference to the DETAILED DESCRIPTION OF THE INVENTION, appended claims, and the accompanying drawing figures.